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Searched refs:CSR_MHPMEVENT5 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/riscv/include/asm/
H A Dencoding.h197 #define CSR_MHPMEVENT5 0x325 macro
/openbmc/qemu/target/riscv/
H A Dcpu_bits.h409 #define CSR_MHPMEVENT5 0x325 macro
H A Dcsr.c5443 [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_mhpmevent,