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Searched refs:CSR_MHPMEVENT3H (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h440 #define CSR_MHPMEVENT3H 0x723 macro
H A Dcsr.c1013 int evt_index = csrno - CSR_MHPMEVENT3H + 3; in read_mhpmeventh()
1023 int evt_index = csrno - CSR_MHPMEVENT3H + 3; in write_mhpmeventh()
5510 [CSR_MHPMEVENT3H] = { "mhpmevent3h", sscofpmf_32, read_mhpmeventh,