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Searched refs:CSR_CYCLE (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/riscv/include/asm/
H A Dencoding.h321 #define CSR_CYCLE 0xc00 macro
/openbmc/qemu/target/riscv/
H A Dcpu_bits.h73 #define CSR_CYCLE 0xc00 macro
H A Dcsr.c116 int base_csrno = CSR_CYCLE; in ctr()
126 if ((csrno >= CSR_CYCLE && csrno <= CSR_INSTRET) || in ctr()
1414 } else if (csrno >= CSR_CYCLE && csrno <= CSR_HPMCOUNTER31) { in read_hpmcounter()
1415 ctr_index = csrno - CSR_CYCLE; in read_hpmcounter()
5826 [CSR_CYCLE] = { "cycle", ctr, read_hpmcounter },