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Searched refs:CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h3183 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x00000010 macro
H A Dgfx_7_2_sh_mask.h2582 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 macro
H A Dgfx_8_1_sh_mask.h3668 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 macro
H A Dgfx_8_0_sh_mask.h3146 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h19402 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT … macro
H A Dgc_9_1_sh_mask.h20713 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h20640 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h22768 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h12867 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h26790 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h27315 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h29290 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h25576 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT … macro