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Searched refs:CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h3177 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x00000018 macro
H A Dgfx_7_2_sh_mask.h2586 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 macro
H A Dgfx_8_1_sh_mask.h3672 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 macro
H A Dgfx_8_0_sh_mask.h3150 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h19404 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT … macro
H A Dgc_9_1_sh_mask.h20715 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h20642 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h22770 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h12869 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h26792 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h27317 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h29292 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h25578 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT … macro