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Searched refs:CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2889 #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x00000000 macro
H A Dgfx_7_2_sh_mask.h3156 #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 macro
H A Dgfx_8_0_sh_mask.h3770 #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 macro
H A Dgfx_8_1_sh_mask.h4292 #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h1257 #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h1123 #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT … macro
H A Dgc_9_1_sh_mask.h1156 #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h1173 #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h1756 #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h6598 #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h7373 #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h6739 #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h7005 #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT … macro