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Searched refs:CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_1_sh_mask.h2394 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10 macro
H A Dgfx_8_0_sh_mask.h1872 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11191 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT … macro
H A Dgc_9_1_sh_mask.h12672 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h12470 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h14288 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h2579 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h15603 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h18150 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h17758 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h16501 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT … macro