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Searched refs:CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_1_sh_mask.h2389 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x400 macro
H A Dgfx_8_0_sh_mask.h1867 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x400 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11199 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK … macro
H A Dgc_9_1_sh_mask.h12680 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK … macro
H A Dgc_9_2_1_sh_mask.h12478 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK … macro
H A Dgc_9_4_3_sh_mask.h14296 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK … macro
H A Dgc_9_4_2_sh_mask.h2587 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK … macro
H A Dgc_11_0_0_sh_mask.h15615 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK … macro
H A Dgc_10_1_0_sh_mask.h18162 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK … macro
H A Dgc_11_0_3_sh_mask.h17770 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK … macro
H A Dgc_10_3_0_sh_mask.h16513 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK … macro