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Searched refs:CP_MEC_CNTL__MEC_ME2_HALT_MASK (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c2635 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v7_0_cp_compute_enable()
4625 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); in gfx_v7_0_soft_reset()
H A Dgfx_v9_4_3.c1388 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v9_4_3_xcc_cp_compute_enable()
H A Dgfx_v10_0.c6215 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v10_0_cp_compute_enable()
6220 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v10_0_cp_compute_enable()
H A Dgfx_v8_0.c4295 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v8_0_cp_compute_enable()
H A Dgfx_v9_0.c3172 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v9_0_cp_compute_enable()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h2221 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000 macro
H A Dgfx_8_0_sh_mask.h2767 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000 macro
H A Dgfx_8_1_sh_mask.h3289 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h846 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK … macro
H A Dgc_9_2_1_sh_mask.h734 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK … macro
H A Dgc_9_1_sh_mask.h745 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK … macro
H A Dgc_9_4_3_sh_mask.h784 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK … macro
H A Dgc_9_4_2_sh_mask.h1367 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK … macro
H A Dgc_11_0_0_sh_mask.h23998 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK … macro
H A Dgc_11_0_3_sh_mask.h26344 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK … macro
H A Dgc_10_1_0_sh_mask.h6325 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK … macro
H A Dgc_10_3_0_sh_mask.h6898 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK … macro