Searched refs:CP_MEC_CNTL (Results 1 – 4 of 4) sorted by relevance
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
H A D | smu8_smumgr.c | 193 tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1); in smu8_load_mec_firmware() 194 tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1); in smu8_load_mec_firmware()
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/openbmc/linux/drivers/gpu/drm/radeon/ |
H A D | cikd.h | 1094 #define CP_MEC_CNTL 0x8234 macro 1098 #define CP_MEC_CNTL 0x8234 macro
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H A D | cik.c | 4220 WREG32(CP_MEC_CNTL, 0); in cik_cp_compute_enable() 4231 WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT)); in cik_cp_compute_enable() 4950 WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT); in cik_gpu_soft_reset() 5154 WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT); in cik_gpu_pci_config_reset()
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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | gfx_v11_0.c | 3369 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); in gfx_v11_0_cp_compute_enable() 3371 data = REG_SET_FIELD(data, CP_MEC_CNTL, in gfx_v11_0_cp_compute_enable() 3374 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); in gfx_v11_0_cp_compute_enable() 3375 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); in gfx_v11_0_cp_compute_enable()
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