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Searched refs:CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2380 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L macro
H A Dgfx_7_2_sh_mask.h1187 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 macro
H A Dgfx_8_1_sh_mask.h2039 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 macro
H A Dgfx_8_0_sh_mask.h1515 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11009 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h12490 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h12294 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK … macro
H A Dgc_9_4_3_sh_mask.h14019 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK … macro
H A Dgc_9_4_2_sh_mask.h2310 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h15423 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h17954 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h17578 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h16218 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK … macro