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Searched refs:CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h2101 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000 macro
H A Dgfx_8_1_sh_mask.h3143 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000 macro
H A Dgfx_8_0_sh_mask.h2621 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h691 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK … macro
H A Dgc_9_1_sh_mask.h590 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK … macro
H A Dgc_9_2_1_sh_mask.h579 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK … macro
H A Dgc_9_4_3_sh_mask.h620 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK … macro
H A Dgc_9_4_2_sh_mask.h1209 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK … macro
H A Dgc_11_0_0_sh_mask.h6069 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK … macro
H A Dgc_10_1_0_sh_mask.h6126 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK … macro
H A Dgc_11_0_3_sh_mask.h6844 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK … macro
H A Dgc_10_3_0_sh_mask.h6379 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK … macro