Searched refs:CPUINFO_ZBB (Results 1 – 4 of 4) sorted by relevance
76 #define TCG_TARGET_HAS_rot_i32 (cpuinfo & CPUINFO_ZBB)91 #define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB)92 #define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB)94 #define TCG_TARGET_HAS_andc_i32 (cpuinfo & CPUINFO_ZBB)95 #define TCG_TARGET_HAS_orc_i32 (cpuinfo & CPUINFO_ZBB)96 #define TCG_TARGET_HAS_eqv_i32 (cpuinfo & CPUINFO_ZBB)99 #define TCG_TARGET_HAS_clz_i32 (cpuinfo & CPUINFO_ZBB)100 #define TCG_TARGET_HAS_ctz_i32 (cpuinfo & CPUINFO_ZBB)101 #define TCG_TARGET_HAS_ctpop_i32 (cpuinfo & CPUINFO_ZBB)110 #define TCG_TARGET_HAS_rot_i64 (cpuinfo & CPUINFO_ZBB)[all …]
881 if (cpuinfo & CPUINFO_ZBB) {901 if (cpuinfo & CPUINFO_ZBB) {911 if (cpuinfo & CPUINFO_ZBB) {
39 unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND | CPUINFO_ZVE64X; in cpuinfo_init()51 info |= CPUINFO_ZBB; in cpuinfo_init()73 info |= pair.value & RISCV_HWPROBE_EXT_ZBB ? CPUINFO_ZBB : 0; in cpuinfo_init()74 left &= ~(CPUINFO_ZBA | CPUINFO_ZBB); in cpuinfo_init()111 if (left & CPUINFO_ZBB) { in cpuinfo_init()116 info |= got_sigill ? 0 : CPUINFO_ZBB; in cpuinfo_init()117 left &= ~CPUINFO_ZBB; in cpuinfo_init()
11 #define CPUINFO_ZBB (1u << 2) macro