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Searched refs:CPM_CLKGR0_DDR0 (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c261 #define CPM_CLKGR0_DDR0 BIT(30) macro
435 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_DDR0); in ddr_mux_select()