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Searched refs:CPLL_HZ (Results 1 – 9 of 9) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3328.h52 #define CPLL_HZ (594 * MHz) macro
H A Dcru_rk3188.h13 #define CPLL_HZ (384 * 1000000) macro
H A Dcru_rk3399.h75 #define CPLL_HZ (384*MHz) macro
H A Dcru_rk3288.h15 #define CPLL_HZ (384 * 1000000) macro
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3368.c39 #define CPLL_HZ (400 * 1000 * 1000) macro
54 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
210 { .mux = MMC_PLL_SEL_CPLL, .rate = CPLL_HZ }, in rk3368_mmc_find_best_rate_and_parent()
333 pll_rate = CPLL_HZ; in rk3368_gmac_set_clk()
H A Dclk_rk3288.c142 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
319 pll_rate = CPLL_HZ; in rockchip_mac_set_clk()
842 div = CPLL_HZ / rate; in rk3288_clk_set_rate()
843 assert((div - 1 < 64) && (div * rate == CPLL_HZ)); in rk3288_clk_set_rate()
H A Dclk_rk3328.c38 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1);
425 pll_rate = CPLL_HZ; in rk3328_gmac2io_set_clk()
H A Dclk_rk3399.c51 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
698 div = CPLL_HZ / aclk_vop; in rk3399_vop_set_clk()
H A Dclk_rk3188.c82 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);