Searched refs:CPLL (Results 1 – 7 of 7) sorted by relevance
| /openbmc/linux/arch/arm/boot/dts/samsung/ |
| H A D | exynos5422-odroid-core.dtsi | 71 /* derived from 666MHz CPLL */
89 /* derived from 666MHz CPLL */
116 /* derived from 666MHz CPLL */
155 /* derived from 666MHz CPLL */
164 /* derived from 666MHz CPLL */
221 /* derived from 666MHz CPLL */
281 /* derived from 666MHz CPLL */
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| /openbmc/u-boot/arch/arm/mach-exynos/include/mach/ |
| H A D | clk.h | 18 #define CPLL 8 macro
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| /openbmc/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3368.c | 142 rkclk_set_pll(cru, CPLL, &cpll_init_cfg); in rkclk_init()
148 cpll = rkclk_pll_get_rate(cru, CPLL); in rkclk_init()
185 pll_rate = rkclk_pll_get_rate(cru, CPLL); in rk3368_mmc_get_clk()
460 rate = rkclk_pll_get_rate(priv->cru, CPLL); in rk3368_clk_get_rate()
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | xlnx-versal-clk.h | 35 #define CPLL 26 macro
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rk3368.h | 17 CPLL, enumerator
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| /openbmc/u-boot/arch/arm/mach-exynos/ |
| H A D | clock.c | 1049 const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL, in exynos5800_get_lcd_clk()
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| /openbmc/linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3328.dtsi | 795 * CPLL should run at 1200, but that is to high for
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