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Searched refs:CPHA (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dqca,qca7000.txt51 spi-cpha; /* SPI mode: CPHA=1 */
/openbmc/linux/Documentation/spi/
H A Dspi-summary.rst105 - CPHA indicates the clock phase used to sample data; CPHA=0 says
106 sample on the leading edge, CPHA=1 means the trailing edge.
108 Since the signal needs to stabilize before it's sampled, CPHA=0
113 but their timing diagrams will make the CPOL and CPHA modes clear.
115 In the SPI mode number, CPOL is the high order bit and CPHA is the
118 trailing clock edge (CPHA=1), that's SPI mode 1.
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dspi-controller.yaml108 The device requires shifted clock phase (CPHA) mode.
/openbmc/u-boot/doc/device-tree-bindings/spi/
H A Dspi-bus.txt53 shifted clock phase (CPHA) mode
/openbmc/linux/drivers/spi/
H A Dspi-geni-qcom.c22 #define CPHA BIT(0) macro
413 cpha = CPHA; in setup_fifo_params()
/openbmc/qemu/hw/char/
H A Dstm32l4x5_usart.c72 FIELD(CR2, CPHA, 9, 1) /* Clock phase */