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Searched refs:CPG_PLL2CR (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/clk/renesas/
H A Dclk-r8a73a4.c29 #define CPG_PLL2CR 0x2c macro
114 cr = CPG_PLL2CR; in r8a73a4_cpg_register_clock()
H A Dclk-sh73a0.c31 #define CPG_PLL2CR 0x2c macro
102 enable_reg += CPG_PLL2CR; in sh73a0_cpg_register_clock()
H A Drcar-gen3-cpg.c34 #define CPG_PLL2CR 0x002c macro
387 base, 2, CPG_PLL2CR, 2); in rcar_gen3_cpg_clk_register()
/openbmc/u-boot/drivers/clk/renesas/
H A Dclk-rcar-gen3.c28 #define CPG_PLL2CR 0x002c macro
229 value = readl(priv->base + CPG_PLL2CR); in gen3_clk_get_rate64()