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Searched refs:CPG_PL5_SDIV_DIV_DSI_B_WEN (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/clk/renesas/
H A Drzg2l-cpg.h41 #define CPG_PL5_SDIV_DIV_DSI_B_WEN BIT(24) macro
H A Drzg2l-cpg.c372 writel(CPG_PL5_SDIV_DIV_DSI_A_WEN | CPG_PL5_SDIV_DIV_DSI_B_WEN | in rzg2l_cpg_dsi_div_set_rate()