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Searched refs:CPG_PL5_SDIV (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/clk/renesas/
H A Drzg2l-cpg.h27 #define CPG_PL5_SDIV (0x420) macro
H A Drzg2l-cpg.c375 priv->base + CPG_PL5_SDIV); in rzg2l_cpg_dsi_div_set_rate()