Searched refs:CPG_FRQCRA (Results 1 – 3 of 3) sorted by relevance
| /openbmc/linux/drivers/clk/renesas/ |
| H A D | clk-r8a73a4.c | 24 #define CPG_FRQCRA 0x00 macro
42 { "i", CPG_FRQCRA, 20 },
43 { "m3", CPG_FRQCRA, 12 },
44 { "b", CPG_FRQCRA, 8 },
45 { "m1", CPG_FRQCRA, 4 },
46 { "m2", CPG_FRQCRA, 0 },
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| H A D | clk-r8a7740.c | 23 #define CPG_FRQCRA 0x00 macro
39 { "i", CPG_FRQCRA, 20, CLK_ENABLE_ON_INIT },
40 { "zg", CPG_FRQCRA, 16, CLK_ENABLE_ON_INIT },
41 { "b", CPG_FRQCRA, 8, CLK_ENABLE_ON_INIT },
42 { "m1", CPG_FRQCRA, 4, CLK_ENABLE_ON_INIT },
102 u32 value = readl(base + CPG_FRQCRA); in r8a7740_cpg_register_clock()
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| H A D | clk-sh73a0.c | 23 #define CPG_FRQCRA 0x00 macro
47 { "zg", "pll0", CPG_FRQCRA, 16 },
48 { "m3", "pll1", CPG_FRQCRA, 12 },
49 { "b", "pll1", CPG_FRQCRA, 8 },
50 { "m1", "pll1", CPG_FRQCRA, 4 },
51 { "m2", "pll1", CPG_FRQCRA, 0 },
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