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Searched refs:CP0_WatchHi (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/target/mips/tcg/sysemu/
H A Dcp0_helper.c419 return (int32_t) env->CP0_WatchHi[sel]; in helper_mfc0_watchhi()
424 return env->CP0_WatchHi[sel] >> 32; in helper_mfhc0_watchhi()
497 return env->CP0_WatchHi[sel]; in helper_dmfc0_watchhi()
1336 uint64_t m_bit = env->CP0_WatchHi[sel] & (1 << CP0WH_M); /* read-only */ in helper_mtc0_watchhi()
1340 env->CP0_WatchHi[sel] = m_bit | (arg1 & mask); in helper_mtc0_watchhi()
1341 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7); in helper_mtc0_watchhi()
1346 env->CP0_WatchHi[sel] = ((uint64_t) (arg1) << 32) | in helper_mthc0_watchhi()
1347 (env->CP0_WatchHi[sel] & 0x00000000ffffffffULL); in helper_mthc0_watchhi()
/openbmc/qemu/target/mips/
H A Dcpu.c323 env->CP0_WatchHi[i] = 1 << CP0WH_M; in mips_cpu_reset_hold()
326 env->CP0_WatchHi[7] = 0; in mips_cpu_reset_hold()
H A Dcpu.h1006 uint64_t CP0_WatchHi[8]; member
/openbmc/qemu/target/mips/sysemu/
H A Dmachine.c310 VMSTATE_UINT64_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
/openbmc/qemu/target/mips/tcg/
H A Dtranslate.c5181 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_WatchHi[sel]), 0); in gen_mfhc0()