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Searched refs:CP0_WATCHLO (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/mips/cpu/
H A Dstart.S39 MTC0 zero, CP0_WATCHLO,\sel
194 MTC0 zero, CP0_WATCHLO
/openbmc/u-boot/arch/mips/include/asm/
H A Dmipsregs.h62 #define CP0_WATCHLO $18 macro
/openbmc/linux/arch/mips/include/asm/
H A Dmipsregs.h83 #define CP0_WATCHLO $18 macro