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Searched refs:CP0_CMGCRBase (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/hw/mips/
H A Dcps.c145 gcr_base = MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4; in mips_cps_realize()
/openbmc/qemu/hw/misc/
H A Dmips_cmgcr.c42 mips_cpu->env.CP0_CMGCRBase = gcr->gcr_base >> 4; in update_gcr_base()
/openbmc/qemu/target/mips/sysemu/
H A Dmachine.c296 VMSTATE_UINTTL(env.CP0_CMGCRBase, MIPSCPU),
/openbmc/qemu/target/mips/
H A Dcpu.h831 target_ulong CP0_CMGCRBase; member
H A Dcpu.c302 env->CP0_CMGCRBase = 0x1fbf8000 >> 4; in mips_cpu_reset_hold()
/openbmc/qemu/target/mips/tcg/
H A Dtranslate.c5742 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_CMGCRBase)); in gen_mfc0()
7219 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_CMGCRBase)); in gen_dmfc0()