Home
last modified time | relevance | path

Searched refs:CP0C5_GI (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu-defs.c.inc760 (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI),
800 (1 << CP0C5_LLB) | (1 << CP0C5_MRP) | (3 << CP0C5_GI),
H A Dcpu.h940 #define CP0C5_GI 15 /* 16..15 */ macro
/openbmc/qemu/target/mips/tcg/
H A Dtranslate.c15096 ctx->gi = (env->CP0_Config5 >> CP0C5_GI) & 3; in mips_tr_init_disas_context()