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Searched refs:CP0C3_MSAP (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu-defs.c.inc437 (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
481 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_MSAP) |
754 (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
795 (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
907 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
H A Dcpu.h887 #define CP0C3_MSAP 28 macro
1328 return env->CP0_Config3 & (1 << CP0C3_MSAP); in ase_msa_available()