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Searched refs:CP0C3_ISA (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu.c406 if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) { in mips_cpu_reset_hold()
H A Dcpu-defs.c.inc381 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt) |
406 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt) |
482 (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) |
519 (1 << CP0C3_ISA_ON_EXC) | (1 << CP0C3_ISA) |
H A Dcpu.h898 #define CP0C3_ISA 14 /* 15..14 */ macro