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Searched refs:CP0C3_CMGCR (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu.c301 if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) { in mips_cpu_reset_hold()
667 return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; in cpu_type_supports_cps_smp()
H A Dcpu-defs.c.inc437 (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
517 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) |
752 (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
792 (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
H A Dcpu.h887 #define CP0C3_CMGCR 29 macro
/openbmc/qemu/target/mips/tcg/
H A Dtranslate.c15337 ctx->cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1; in mips_tr_init_disas_context()