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Searched refs:CP0C1_DL (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/mips/
H A Dcpu-defs.c.inc64 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
86 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
106 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
126 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
146 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
167 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
188 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
209 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
231 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
253 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
[all …]
H A Dcpu.h864 #define CP0C1_DL 10 /* 12..10 */ macro
/openbmc/qemu/target/mips/tcg/
H A Dtranslate.c1716 !(ctx->CP0_Config1 & (1 << CP0C1_DL)) && in check_nms_dl_il_sl_tl_l2c()