Searched refs:CORE_SSI_DIV (Results 1 – 2 of 2) sorted by relevance
168 0x00000F00, CORE_SSI_DIV << 8); in dpll3_init_34xx()217 clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8); in dpll3_init_34xx()418 0x00000F00, CORE_SSI_DIV << 8); in dpll3_init_36xx()467 clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8); in dpll3_init_36xx()
23 #define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ macro