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Searched refs:CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h11489 #define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x1 macro
H A Ddce_10_0_sh_mask.h12591 #define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x1 macro
H A Ddce_11_0_sh_mask.h12597 #define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x1 macro
H A Ddce_11_2_sh_mask.h13213 #define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x1 macro
H A Ddce_12_0_sh_mask.h56059 #define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h27088 #define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK … macro
H A Ddcn_1_0_sh_mask.h932 #define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK … macro
H A Ddcn_3_0_1_sh_mask.h200 #define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK … macro
H A Ddcn_3_2_1_sh_mask.h47828 #define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK … macro
H A Ddcn_3_1_5_sh_mask.h51029 #define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK … macro
H A Ddcn_3_0_2_sh_mask.h54135 #define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK … macro
H A Ddcn_2_0_0_sh_mask.h59131 #define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK … macro
H A Ddcn_3_0_0_sh_mask.h62713 #define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK … macro
H A Ddcn_3_2_0_sh_mask.h47830 #define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK … macro