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Searched refs:CONFIG_SYS_DDR_TIMING_5_1333 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/include/configs/
H A DBSC9132QDS.h141 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 macro
177 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333
/openbmc/u-boot/board/freescale/bsc9132qds/
H A Dspl_minimal.c59 __raw_writel(CONFIG_SYS_DDR_TIMING_5_1333, &ddr->timing_cfg_5); in sdram_init()
/openbmc/u-boot/scripts/
H A Dconfig_whitelist.txt2419 CONFIG_SYS_DDR_TIMING_5_1333