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Searched refs:CONFIG_SYS_DDR_TIMING_1_1333 (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/board/freescale/bsc9132qds/
H A Dspl_minimal.c50 __raw_writel(CONFIG_SYS_DDR_TIMING_1_1333, &ddr->timing_cfg_1); in sdram_init()
H A Dddr.c50 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1333,
/openbmc/u-boot/include/configs/
H A DBSC9132QDS.h155 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 macro
/openbmc/u-boot/scripts/
H A Dconfig_whitelist.txt2397 CONFIG_SYS_DDR_TIMING_1_1333