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Searched refs:CNVC_SURFACE_PIXEL_FORMAT (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_ipp.h36 SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
80 IPP_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
147 type CNVC_SURFACE_PIXEL_FORMAT; \
185 uint32_t CNVC_SURFACE_PIXEL_FORMAT; member
H A Ddcn10_dpp.c380 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp1_cnv_setup()
381 CNVC_SURFACE_PIXEL_FORMAT, pixel_format); in dpp1_cnv_setup()
H A Ddcn10_dpp_cm.c710 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp1_full_bypass()
711 CNVC_SURFACE_PIXEL_FORMAT, 0x8); in dpp1_full_bypass()
H A Ddcn10_dpp.h121 SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
328 TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
1074 type CNVC_SURFACE_PIXEL_FORMAT; \
1343 uint32_t CNVC_SURFACE_PIXEL_FORMAT; \
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_dpp.c166 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp201_cnv_setup()
167 CNVC_SURFACE_PIXEL_FORMAT, pixel_format); in dpp201_cnv_setup()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dpp.c225 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp2_cnv_setup()
226 CNVC_SURFACE_PIXEL_FORMAT, pixel_format); in dpp2_cnv_setup()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dpp.h136 SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
301 TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
H A Ddcn30_dpp.c307 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp3_cnv_setup()
308 CNVC_SURFACE_PIXEL_FORMAT, pixel_format, in dpp3_cnv_setup()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_resource.h523 SRI_ARR(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \