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Searched refs:CNTX_BUSY_INT_ENABLE (Results 1 – 15 of 15) sorted by relevance

/openbmc/linux/drivers/gpu/drm/radeon/
H A Dnid.h495 # define CNTX_BUSY_INT_ENABLE (1 << 19) macro
H A Dsid.h1279 # define CNTX_BUSY_INT_ENABLE (1 << 19) macro
H A Dcikd.h1332 # define CNTX_BUSY_INT_ENABLE (1 << 19) macro
H A Dsi.c5152 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in si_enable_gui_idle_interrupt()
5154 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in si_enable_gui_idle_interrupt()
5953 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in si_disable_interrupt_state()
6071 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in si_irq_set()
H A Devergreen.c4467 CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in evergreen_disable_interrupt_state()
4473 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in evergreen_disable_interrupt_state()
4496 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; in evergreen_irq_set()
H A Devergreend.h1247 # define CNTX_BUSY_INT_ENABLE (1 << 19) macro
H A Dcik.c5763 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in cik_enable_gui_idle_interrupt()
5765 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in cik_enable_gui_idle_interrupt()
6860 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in cik_disable_interrupt_state()
7038 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in cik_irq_set()
H A Dr600d.h715 # define CNTX_BUSY_INT_ENABLE (1 << 19) macro
H A Dr600.c3622 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in r600_disable_interrupt_state()
3763 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; in r600_irq_set()
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsid.h1307 # define CNTX_BUSY_INT_ENABLE (1 << 19) macro
H A Dgfx_v11_0.c1753 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, in gfx_v11_0_enable_gui_idle_interrupt()
4442 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); in gfx_v11_0_soft_reset()
4542 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); in gfx_v11_0_soft_reset()
4881 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); in gfx_v11_0_update_coarse_grain_clock_gating()
H A Dgfx_v9_4_3.c1167 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_4_3_xcc_enable_gui_idle_interrupt()
H A Dgfx_v8_0.c3858 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
H A Dgfx_v9_0.c2474 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt()
H A Dgfx_v10_0.c5018 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, in gfx_v10_0_enable_gui_idle_interrupt()