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Searched refs:CMU_REG1_PLL_CP_SEL_SET (Results 1 – 1 of 1) sorted by relevance

/openbmc/linux/drivers/phy/
H A Dphy-xgene.c137 #define CMU_REG1_PLL_CP_SEL_SET(dst, src) \ macro
787 val = CMU_REG1_PLL_CP_SEL_SET(val, 0x5); in xgene_phy_sata_cfg_cmu_core()
789 val = CMU_REG1_PLL_CP_SEL_SET(val, 0x3); in xgene_phy_sata_cfg_cmu_core()