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Searched refs:CLK_VPP0_GALS_VPP1_WPESYS (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8188-vpp0.c76 GATE_VPP0_1(CLK_VPP0_GALS_VPP1_WPESYS, "vpp0_gals_vpp1_wpesys", "top_vpp", 21),
/openbmc/linux/include/dt-bindings/clock/
H A Dmediatek,mt8188-clk.h390 #define CLK_VPP0_GALS_VPP1_WPESYS 31 macro