Home
last modified time | relevance | path

Searched refs:CLK_TOP_TVDPLL_D4 (Results 1 – 22 of 22) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dmt8167-clk.h35 #define CLK_TOP_TVDPLL_D4 (CLK_TOP_NR_CLK + 11) macro
H A Dmt6797-clk.h98 #define CLK_TOP_TVDPLL_D4 88 macro
H A Dmediatek,mt6795-clk.h67 #define CLK_TOP_TVDPLL_D4 56 macro
H A Dmt8173-clk.h69 #define CLK_TOP_TVDPLL_D4 59 macro
H A Dmt2712-clk.h105 #define CLK_TOP_TVDPLL_D4 74 macro
H A Dmt6779-clk.h93 #define CLK_TOP_TVDPLL_D4 83 macro
H A Dmt8183-clk.h118 #define CLK_TOP_TVDPLL_D4 82 macro
H A Dmt8186-clk.h126 #define CLK_TOP_TVDPLL_D4 107 macro
H A Dmt2701-clk.h59 #define CLK_TOP_TVDPLL_D4 49 macro
H A Dmt8192-clk.h133 #define CLK_TOP_TVDPLL_D4 121 macro
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7623.c153 FACTOR0(CLK_TOP_TVDPLL_D4, CLK_APMIXED_TVDPLL, 1, 4),
324 CLK_TOP_TVDPLL_D4
331 CLK_TOP_TVDPLL_D4
/openbmc/u-boot/include/dt-bindings/clock/
H A Dmt7623-clk.h75 #define CLK_TOP_TVDPLL_D4 62 macro
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt6795-topckgen.c422 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_594m", 1, 4),
H A Dclk-mt8186-topckgen.c61 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
H A Dclk-mt8173-topckgen.c501 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_594m", 1, 4),
H A Dclk-mt8167.c80 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4),
H A Dclk-mt6797.c78 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4),
H A Dclk-mt8183.c81 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
H A Dclk-mt2712.c112 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4),
H A Dclk-mt8192.c79 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
H A Dclk-mt6779.c79 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
H A Dclk-mt2701.c110 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),