Searched refs:CLK_TOP_SYSPLL (Results 1 – 8 of 8) sorted by relevance
| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | mt6765-clk.h | 35 #define CLK_TOP_SYSPLL 0 macro
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| H A D | mt2712-clk.h | 35 #define CLK_TOP_SYSPLL 4 macro
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| H A D | mt2701-clk.h | 11 #define CLK_TOP_SYSPLL 1 macro
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| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | mt7623-clk.h | 28 #define CLK_TOP_SYSPLL 15 macro
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| /openbmc/u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7623.c | 101 FACTOR0(CLK_TOP_SYSPLL, CLK_APMIXED_MAINPLL, 1, 1),
727 .fdivs_offs = CLK_TOP_SYSPLL,
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| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt2712.c | 43 FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
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| H A D | clk-mt6765.c | 83 FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
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| H A D | clk-mt2701.c | 57 FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
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