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Searched refs:CLK_TOP_SNPS_ETH_50M_RMII (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dmediatek,mt8188-clk.h78 #define CLK_TOP_SNPS_ETH_50M_RMII 67 macro
H A Dmt8195-clk.h96 #define CLK_TOP_SNPS_ETH_50M_RMII 84 macro
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8188-topckgen.c1118 MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII, "snps_eth_50m_rmii",
H A Dclk-mt8195-topckgen.c1071 MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII, "snps_eth_50m_rmii",
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8195.dtsi1261 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>,
1265 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;