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Searched refs:CLK_TOP_SENINF_SEL (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dmt6765-clk.h157 #define CLK_TOP_SENINF_SEL 122 macro
H A Dmt8192-clk.h49 #define CLK_TOP_SENINF_SEL 37 macro
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8192.c635 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel",
H A Dclk-mt6765.c454 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel", seninf_parents,