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Searched refs:CLK_TOP_PWM_INFRA_SEL (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dmt2712-clk.h194 #define CLK_TOP_PWM_INFRA_SEL 163 macro
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt2712.c744 MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel", pwm_parents, 0x560, 8, 2, 15),