Searched refs:CLK_TOP_PE2_MAC_P1_SEL (Results 1 – 4 of 4) sorted by relevance
163 #define CLK_TOP_PE2_MAC_P1_SEL 132 macro
698 MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel", pe2_mac_p0_parents,
160 clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
934 clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,