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Searched refs:CLK_TOP_MUX_UART (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dmt6797-clk.h22 #define CLK_TOP_MUX_UART 12 macro
H A Dmt8183-clk.h41 #define CLK_TOP_MUX_UART 5 macro
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt6797.c338 MUX_GATE(CLK_TOP_MUX_UART, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
H A Dclk-mt8183.c491 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel",