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Searched refs:CLK_TOP_MUX_PWM (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dmt6797-clk.h17 #define CLK_TOP_MUX_PWM 7 macro
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt6797.c333 MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7),