| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | mt6797-clk.h | 103 #define CLK_TOP_MSDCPLL_D4 93 macro
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| H A D | mediatek,mt6795-clk.h | 47 #define CLK_TOP_MSDCPLL_D4 36 macro
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| H A D | mt8173-clk.h | 49 #define CLK_TOP_MSDCPLL_D4 39 macro
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| H A D | mt2712-clk.h | 112 #define CLK_TOP_MSDCPLL_D4 81 macro
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| H A D | mt6779-clk.h | 98 #define CLK_TOP_MSDCPLL_D4 88 macro
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| H A D | mt8183-clk.h | 123 #define CLK_TOP_MSDCPLL_D4 87 macro
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| H A D | mt2701-clk.h | 49 #define CLK_TOP_MSDCPLL_D4 39 macro
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| H A D | mt8192-clk.h | 138 #define CLK_TOP_MSDCPLL_D4 126 macro
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| H A D | mt8195-clk.h | 204 #define CLK_TOP_MSDCPLL_D4 192 macro
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| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | mt7623-clk.h | 66 #define CLK_TOP_MSDCPLL_D4 53 macro
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| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt6795-topckgen.c | 400 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
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| H A D | clk-mt8173-topckgen.c | 479 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
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| H A D | clk-mt6797.c | 83 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, 4),
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| H A D | clk-mt8183.c | 96 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
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| H A D | clk-mt2712.c | 119 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, 4),
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| H A D | clk-mt8192.c | 84 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
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| H A D | clk-mt8195-topckgen.c | 106 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
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| H A D | clk-mt6779.c | 98 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
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| H A D | clk-mt2701.c | 98 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
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| /openbmc/u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7623.c | 141 FACTOR0(CLK_TOP_MSDCPLL_D4, CLK_APMIXED_MSDCPLL, 1, 4),
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