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Searched refs:CLK_TOP_MSDC50_0_H_SEL (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dmediatek,mt6795-clk.h103 #define CLK_TOP_MSDC50_0_H_SEL 92 macro
H A Dmt8173-clk.h105 #define CLK_TOP_MSDC50_0_H_SEL 95 macro
H A Dmt8192-clk.h35 #define CLK_TOP_MSDC50_0_H_SEL 23 macro
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt6795-topckgen.c471 TOP_MUX_GATE(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents,
H A Dclk-mt8173-topckgen.c550 MUX_GATE_FLAGS(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents,
H A Dclk-mt8192.c602 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel",
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dmtk-sd.yaml319 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt6795.dtsi644 <&topckgen CLK_TOP_MSDC50_0_H_SEL>,
H A Dmt8173.dtsi888 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;