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Searched refs:CLK_TOP_MFG_PLL_SEL (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8192.c582 MUX_CLR_SET_UPD(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel",
977 if (top_mtk_muxes[i].id == CLK_TOP_MFG_PLL_SEL) in clk_mt8192_reg_mfg_mux_notifier()
1012 .mfg_clk_idx = CLK_TOP_MFG_PLL_SEL,
/openbmc/linux/include/dt-bindings/clock/
H A Dmt8192-clk.h26 #define CLK_TOP_MFG_PLL_SEL 14 macro
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8192.dtsi519 clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>,