Searched refs:CLK_TOP_EMMC_HCLK_SEL (Results 1 – 4 of 4) sorted by relevance
| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | mt7623-clk.h | 126 #define CLK_TOP_EMMC_HCLK_SEL 112 macro
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | mt2701-clk.h | 110 #define CLK_TOP_EMMC_HCLK_SEL 99 macro
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| /openbmc/u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7623.c | 541 MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, emmc_hclk_parents, 0xA0, 24, 2, 31),
664 GATE_PERI0(CLK_PERI_MSDC50_3, CLK_TOP_EMMC_HCLK_SEL, 17),
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| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt2701.c | 543 MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, "emmc_hclk_sel", emmc_hclk_parents,
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