Searched refs:CLK_TOP_AUDPLL_MUX_SEL (Results 1 – 4 of 4) sorted by relevance
| /openbmc/u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7623.c | 169 FACTOR1(CLK_TOP_AUDPLL, CLK_TOP_AUDPLL_MUX_SEL, 1, 1),
170 FACTOR1(CLK_TOP_AUDPLL_D4, CLK_TOP_AUDPLL_MUX_SEL, 1, 4),
171 FACTOR1(CLK_TOP_AUDPLL_D8, CLK_TOP_AUDPLL_MUX_SEL, 1, 8),
172 FACTOR1(CLK_TOP_AUDPLL_D16, CLK_TOP_AUDPLL_MUX_SEL, 1, 16),
173 FACTOR1(CLK_TOP_AUDPLL_D24, CLK_TOP_AUDPLL_MUX_SEL, 1, 24),
571 MUX(CLK_TOP_AUDPLL_MUX_SEL, aud_mux_parents, 0x12c, 6, 3),
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| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | mt7623-clk.h | 148 #define CLK_TOP_AUDPLL_MUX_SEL 134 macro
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | mt2701-clk.h | 133 #define CLK_TOP_AUDPLL_MUX_SEL 122 macro
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| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt2701.c | 594 MUX(CLK_TOP_AUDPLL_MUX_SEL, "audpll_sel", aud_mux_parents,
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